Digital device for checking steady-state value of analogue signal

摘要

A digital device for determining a steady-state value of the analogue signal, comprising an analog-to-digital converter for converting the analogue signal into a numerical pulse code, electrically connected, through a synchronization unit, to inputs of threshold counters, a clock pulse generator electrically connected, through the synchronization unit, to the inputs of the threshold counters and to those of the time interval discriminator, and, through the frequency halver, electrically connected to the inputs of a reversible counter, a digital display unit electrically connected to the digit outputs of the reversible counter. The device also comprises decoders of zero state of the threshold counters, having their inputs respectively connected thereto and their outputs electrically connected to subtract count blocking inputs of the respective threshold counters, to the inputs of the reversible counter and to a control input of the digital display unit. Overflow outputs of the threshold counters are connected to initial setting inputs of the time interval discriminator. An information output of the time interval discriminator is electrically connected to the input, thereof, to the inputs of the threshold counters, to those of the reversible counter and to the control input of the digital display unit. In addition, the device includes seven AND circuits and three NOT circuits by means of which a logical control of electric communication between said units of the device is effected.