| 摘要 |
PURPOSE:To prevent malfunction and runaway of an equipment of the post-stage by fixing a parallel data to a prescribed level during a establishing period from out-of-frame synchronism to frame synchronization. CONSTITUTION:In inputting a coincident detection pulse (h) and a dissidence detection pulse (i) to a hunting pulse generating section 6, a hunting pulse (j) is outputted only when the dissidence detection pulse (i) is outputted to stop the count of a reference pulse generator 1 for one clock period. In inputting the coincidence detection pulse (h) and the dissidence detection pulse (i) to a flip-flop element 9, when the coincidence detection pulse (h) is inputted, an enable signal (m) of logic 1 is outputted and when the dissidence detection pulse (i) is inputted, the enable signal (m) of logic '0' is outputted respectively. In inputting a parallel data to an enable element 10, which is controlled by the enable signal (m), then all recovery data D1-D7 are brought into logical '0' level when the enable signal (m) is logical '0' (state of out-of-frame synchronism) and parallel recovered data D1-D7 are outputted when the enable signal (m) is logical '1' (state of frame synchronization). |
