| 摘要 |
<p>A microprocessor external instruction feature which provides for a single chip microprocessor with on-chip read only instruction store (ROS) that can also be operated with an off-chip instruction store. To accomplish this, the microprocessor instruction sequencing logic (instruction store 10, instruction register 36, instruction counter 38, and sequencing logic 40) is duplicated off-chip by external instruction store 60, instruction register 64, instruction counter 62 and sequency logic 66. The address in counter 62 is generated off-chip and is not transferred from counter 38. An XI MODE input pin signal causes the microprocessor to take its instructions from the external instruction store via 12 XI input pins intead of from the on-chip ROS. A BR DECISION output pin signal from the microprocessor, which indicates that the branch conditions have been met, causes the external instruction counter 62 to be loaded with a branch address from the external instruction register 64 instead of being stepped by external sequencing logic 66. A WAIT output pin signal causes the external instruction feature logic to suspend operations while the microprocessor is in its wait state.</p> |
