| 摘要 |
PURPOSE:To obtain a counting circuit with a versatile resetting function by providing the method of permitting or inhibiting the inputting of the 1st signal, assigning the initial-value setting of the counting circuit, with the 2nd signal. CONSTITUTION:To terminals 1, 2 and 3, clock signal phi, reset signal R and control signal C are input respectively. Now, when signals R and C are both held at level ''0'' while signal phi is input, level ''1'' appears at the output of NOR gate 4 and synchronizing with the fall of signal phi, initial-value setting signal D of level ''1'' is supplied to respective bits of counters 24-29, setting all bits to ''0''. When signals R and C are held at levels ''0'' and ''1'' or ''1'' and ''0'', signal D is held at level ''0'', and consequently the counter is not initialized. Therefore, the inputting of signal R is allowed or inhibited with signal C and when the initialization or temporary holding of counting is required, the initial state of the counter can be placed in a desired state, so that a versatile circuit can be obtained. |
