| 摘要 |
PURPOSE:To improve the processing efficiency for address conversion exception by performing the interruption processing to the address conversion exceptions for each element just with a single address conversion interruption after addition of a factor display identifier. CONSTITUTION:A vector processor contains a main memory access mechanism 2 which performs a reference operation to a main memory 1 by a virtual memory system, an address conversion mechanism 6, a memory mechanism 7, a conversion exception detecting circuit 8, a factor display identifier mechanism 9 for address conversion exceptions, and an interruption mechanism 10 for address conversion exception mode. The mechanism 10 carries out an interruption for address conversion exception in case an address conversion exception is detected to at least a single element after the mechanism 9 added a factor display identifier to each element that produced an address conversion exception.
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