| 摘要 |
PURPOSE:To ensure a high-speed turn-off action for the PNPN-structure memory cell, by providing the N-type gate control transistor which shares the input with the P-type gate control transistor. CONSTITUTION:Signals 1 and 0 are applied to input terminals x and y each in order to give the turn-off to the memory cell formed with PNP and NPN transistors Q1 and Q2. Thus P-type gate control transistor Q3 conducts to draw the current out of the P-type gate which is formed with the collector of Q1 and the base of NPN transistor Q2 each. At the same time, the control is given to N-type gate control transistor Q5 via NPN control transistor Q4 which conducts with signal 1 supplied from terminal y to give the reverse recovery to the N-type gate. Accordingly, the N- type gate receives the reverse recovery simultaneously with the P-type gate. Thus the turn-off time can be reduced to ensure a high-speed turn-off action. |
