| 摘要 |
<p>PURPOSE:To equalize the transmission speed between transmission and receiving, by using clocks of one frequency from the transmission side and by switching clocks successively from the maximum frequency to the minimum frequency for every occurrence of synchronization error and using them as receiving clocks. CONSTITUTION:Start-stop synchronous-system transmission circuit 10 is provided with parallel-series converter 18 which converts parallel transmission data D sent through line 16 to a series data, start bit adding circuit 20, parity check bit adding circuit 22, and stop bit adding circuit 24, and the clock of one frequency out of many kinds of frequency set previously is transmitted from the transmission side to data transmission line 14. Character synchronization errors are detected in stop bit detecting circuit 30 of receiving circuit 12, and clocks CK1-CKn set previously in clock selecting circuit 38 are switched successively for every occurrence of a character synchronization error by selection indicating circuit 40 to select one clock, and this clock is applied to series-parallel converter 32 and is output to line DR after equalizing the transmission speed to transmission circuit 10.</p> |
