摘要 |
An information processing system having a main memory unit, an arithmetic control unit, and a plurality of input/output units, is comprised of a first bus, which is bidirectional, commonly connecting the main memory unit, the arithmetic control unit, and at least one input/output unit, a bus controller for controlling data transfer between two units connecting to the first bus, a second bus, which is also bidirectional, commonly connecting to the arithmetic control unit with at least another input/output unit, and a bus control means which is provided in the arithmetic control unit and controls data transfer between two units connecting to the second bus. The information processing system uses various units connecting to the first and second buses in time sharing and multiplexing mode.
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申请人 |
TOKYO SHIBAURA DENKI KABUSHIKI KAISHA |
发明人 |
ROKUTANDA, TAKASHI;SHIRAOGAWA, YUKIO;NAKAJIMA, YUTAKA;AOYAGI, KEIZO;HIRAOKA, TAKASHI |