Combination capacitor and transistor structure for use in monolithic circuits

摘要

A combination capacitor and transistor structure is described wherein the capacitor is formed integrally with the emitter electrode of the transistor. The transistor is formed in a monolithic integrated circuit using generally known techniques and constitutes a vertically integrated PNP device. The emitter electrode of the transistor which comprises a P+ diffusion region is of a predetermined area which is large enough to form the bottom plate of the capacitor. The top plate of the capacitor is formed by growing a dielectric material over the diffused emitter region and then forming metallization thereover. The combination capacitor and transistor structure may be utilized in a bias network for biasing the output stage of an operational amplifier in a class AB mode. The capacitor formed in the combination structure may be utilized as the compensation capacitor in such operational amplifier which utilizes pole splitting techniques. The improvement provided by the invention reduces the surface area of the semiconductor die chip required to form the capacitor and transistor which facilitates greater device density on a particular die chip.