发明名称 |
Power line disturbance detector circuit |
摘要 |
A power line disturbance (PLD) detector circuit includes a digital counter which is driven by pulses provided by a clock in an associated data processing system. The PLD detector circuit includes a comparator amplifier for comparing primary AC power to a DC reference voltage on a cycle-by-cycle basis. The amplifier generates a reset pulse once during each AC cycle as long as the AC voltage exceeds the DC reference voltage. When a decoder circuit detects a count outside the range of counts attained by the digital counter between normally occurring reset pulses, the decoder circuit responds by generating a PLD signal. The PLD signal is provided both to the associated data processing system and to a Power On Reset circuit. The Power On Reset circuit is initialized by the PLD signal, permitting the circuit to respond consistently upon subsequent restoration of power.
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申请公布号 |
US4245150(A) |
申请公布日期 |
1981.01.13 |
申请号 |
US19790015268 |
申请日期 |
1979.02.26 |
申请人 |
INTERNATIONAL BUSINESS MACHINES CORPORATION |
发明人 |
DRISCOLL, CARLETON D.;HOBBS, JR., JAMES N. |
分类号 |
G01R19/165;G06F1/28;G06F1/30;G06F11/00;H02H3/24;(IPC1-7):G06M3/12 |
主分类号 |
G01R19/165 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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