Low current N-channel logic element FET - has FETs in series providing specified coupling of gate electrodes and positive reference voltage source

摘要

Two f.e.t.s have their gate electrodes connected together and coupled to an input terminal. The transistor input electrodes are at reference potential. To the first f.e.t. (T1) is in series with a third transistor (T2) such that an output terminal (Sa) is connected to the output electrode of the first transistor and to the input electrode of the third transistor. The third transistor gate electrode is connected to the output electrode of the second transistor (T3). The output electrode of the third transistor is coupled to a positive reference voltage source. To the output electrode of the second transistor and to the gate electrode of the third transistor a fourth f.e.t. (T4) and/or two series connected resistors is connected. The fourth transistor input and gate electrodes are interconnected and coupled to the third transistor gate electrode and to the second transistor output electrode.