Semiconductor device having pairs of vertical complementary bipolar transistors and method of fabrication therefor.

摘要

A vertical pair (2) of complementary, bipolar transistors which includes a semiconductor substrate (8) of one conductivity type and a pair of dielectric isolation regions (9, 10) disposed in contiguous relationship with the substrate. An injector region (3) of opposite conductivity type is disposed between the pair of isolation regions (9, 10). A pair of heavily doped polycrystalline semiconductor regions (6, 5) of the one conductivity type is disposed over and in registry with the pair of isolation regions (9, 10). A single crystal semiconductor region (18) of the one conductivity type is disposed over and in registry with the injector region (3). Finally, a first zone (16) of opposite conductivity type is disposed in the single crystal region and a second zone (14) of the one conductivity type is disposed in the first zone (16). To form a memory cell, another vertical pair (2') of complementary, bipolar transistors like those just described is disposed in electrically isolated, spaced relationship with the first mentioned vertical pair (2) of complementary bipolar transistors. These pairs (2, 2') of transistors are arranged so that an isolation region (9) and a polycrystalline region (6) of each are common. To form the memory cell, the first and second zones (16,14; 16', 14') of each of the pairs are cross-coupied.

In addition, a method of manufacturing a semiconductor device having vertical complementary, bipolar transistors which includes the steps of forming regions (9,10) of dielectric isolation which are contiguous with a semiconductor substrate (8) and a region (3) of semiconductor of one conductivity type there-between, the semiconductor substrate (8) being of opposite conductivity type, forming regions (6, 5) of heavily doped, polycrystalline semiconductor of the opposite conductivity type and a region of single crystal semiconductor (18) of the opposite conductivity type in registry with the regions of dielectric isolation (9, 10) and the semiconductor region (18) of one conductivity type, respectively. The method also includes the step of forming a zone (16) of one conductivity type in the region (18) of singly crystal semiconductor and a zone (14) of opposite conductivity type in the zone (16) of one conductivity type. The method may be used to fabricate a buried injector memory cell.