Input/output channel for a high-speed computing system.

摘要

Both byte-multiplexer and selector channels for transfering data between main memory (40) and peripheral data handling devices (51-53) are disclosed. The interface between the channel (20) and the external control unit (50) is the standard (plug-compatible) IBM/System 370 bus/tag interface. The channel (20) includes a CPU interface unit (110) which receives I/O instructions, channel addresses and device addresses and which returns condition codes and interrupt requests to the CPU (30); a memory interface (120) which fetches the channel address word (CAW), channel command words (CCW's) from memory and returns a channel status word (CSW) to memory at the conclusion of an I/O operation, and which (normally) transfers data to and from the memory in four-byte (fullword) units; and an I/O interface unit (130) which transfers device address and status data to and from the connected control unit and which transfers data in one-byte units to and from the control unit. The three interface units communicate with one another over a sixteen-bit (two-byte) internal bus (150) which is also connected to the data ports of a sixteen-bit arithmetic logic unit. (141). The interface units and the ALU are controlled by a micro-sequencing unit (143) which addresses microinstructions stored in a control read-only (142) buffering the data flow between memory (40) and the connected control units (50) and for maintaining updated unit control information for each attached device (51-53).