发明名称 ERROR DETECTION SYSTEM
摘要 PURPOSE:To detect an arithmetic error securely by inputting the same data to subarithmetic units for arithmetic of n-digit data and by comparing arithmetic results from those subarithmetic units by a comparator. CONSTITUTION:To add n-digit data to each other, carry-outs Cout' and Cout'', and sums S0' and Sn-1', and S0'' and Sn-1'' are sent to a comparing circuit by way of the route shown by dotted line. Comparing circuit 3 consists of an exclusive-OR gate. Comparing circuit 3 compares carry-out Cout' to Cout'' first and, when the both disagree, outputs an error detection signal. Then, comparing circuit 2 makes bit by bit comparisons between sums S0' and Sn-1', and S0'' and Sn-1'' and, when a dissident bit is found, outputs the error detection signal. Then, data transfer control is exercised with a microprogram.
申请公布号 JPS55166751(A) 申请公布日期 1980.12.26
申请号 JP19790074320 申请日期 1979.06.13
申请人 FUJITSU LTD 发明人 SHINAGAWA AKIO
分类号 G06F11/18;G06F11/16 主分类号 G06F11/18
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