| 摘要 |
PURPOSE:To reduce delay and a circuit area and to easily execute timing design by connecting each switching circuit for holding data in accordance with the clock level of a pipeline register between plural pipeline stages. CONSTITUTION:Each switching circuits 14, 15 respectively connected between pipeline stages is constituted of an n-channel MOS transistor(TR). An output O from a pipeline register 16 is changed after raising a clock CK and delayed by a pipeline stage 11 to change an input Q to the circuit 14. When the delay of each route up to the stage 11 is within a half and one period of the clock CK, the TR constituting the circuit 14 is in an OFF state, so that the data of the preceding cycle are stored by diffusion capacity or the like. The TR is turned on by the rise of the succeeding clock and new data Q are simultaneously transmitted to a pipeline stage 12. The operation of input and output R, S of the circuit 15 is similarly executed. |
