发明名称 PHASE LOCKED LOOP
摘要 PURPOSE:To provide the phase locked loop in which an output signal frequency is not fluctuated by stopping the phase locking till an input signal comes after an input signal is interrupted. CONSTITUTION:The phase locked loop is provided with a voltage controlled oscillator 6, a phase comparator circuit 2 comparing a phase of an output signal CLK of the voltage controlled oscillator 6 with a phase of an input signal RD to provide a control voltage to the voltage controlled oscillator 6, and control circuits 10a, 10b, 10c activating the phase comparator circuit 2 when the input signal RD is existing and stopping the locking of the phase comparator circuit 2 when the input of the input signal RD is lost for a predetermined time to control the voltage-controlled oscillator 6 so as to be in operation at a predetermined frequency.
申请公布号 JPH06252752(A) 申请公布日期 1994.09.09
申请号 JP19930032130 申请日期 1993.02.22
申请人 FUJITSU LTD;FUJITSU VLSI LTD 发明人 YOSHIKAWA KIMIO
分类号 H03L7/14 主分类号 H03L7/14
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