DATA RATE CONVERTER

摘要

PURPOSE:To prevent missing data due to the underflow of a FIFO from being caused when a pointer is revised for plural number of times in an NDF or the like when a C clock with less jitter is recovered. CONSTITUTION:The converter is provided with an intermittent clock generating circuit 106 in which a FIFO 101 recovering C data from STM data is employed and a discrete pulse equivalent to an SOH byte (including staff byte) is generated to generate a PLL reference signal and a POH pulse and the discrete pulse are synthesized to generate an intermittent clock (GCKC), and when a pointer is changed by an NDF or the like, a PLL reference signal is generated by using the intermittent clock inserting the POH pulse to a position different from a position of the discrete pulse at all times to obtain a read clock from the FIFO 101.