| 摘要 |
PURPOSE:To keep the timing between transmission and reception and input and output at the same timing, by providing the shift register at the input and output section and connecting the part between the input and output and the transmission and reception units with serial buses for the shift register. CONSTITUTION:The reception data of analog signal serially transmitted from the line 1 is received at the reception unit 2, demodulated at the demodulation section 2-1 to produce the digital data. The digital data produced at the demodulation section 2-1 is input to the I/O unit 3 via the serial bus 6 and input to the shift register 3-2 serially. On the other hand, the digital data is serially fed to the data check section 2-2 for the check. The data check section 2-2 produces the reception set (R. SET) signal when all the data check is finished. The R.SET signal is fed to the data memory 3-1 and the content of the shift register 3-2 is parallelly written in the data memory. |
