| 摘要 |
PURPOSE:To obtain the memory circuit to output the DC stable state, by storing and outputting the AC exciting state only with the application of a single set pulse and releasing the storage with the application of the reset pulse. CONSTITUTION:When a signal set pulse S is input to the terminal T of D type FFF1 at time t1, the output Q1 is given to the NOR gate N1, the output Q3 is at 1 and the shift register SR is possible for usage. Further, when the pulse T1 of the clock pulse CL is fed to the terminal T at time t2, the output Q4 is produced at the terminal A and the output Q of the NOR gate N2 is changed to 0. The output Q4 is fed to FFF1, F2, which are respectively reset and the output of the NOR gate N1 is 0, and the output Q is in AC exciting state in the frequency a half the clock pulse CL according to the clock pulse. At time t9, when the reset pulse R is fed, the shift register 2 is reset, the output Q is 1, and DC stable state is obtained. |
