发明名称 WATCH MALFUNCTION PREVENTING SYSTEM
摘要 PURPOSE:To prevent the watch malfunction at the data transfer time with a simple constitution, by inhibiting the data transfer to the dividing counter while the operation is carried out based on the count output of the dividing counter and with the control given to the gate. CONSTITUTION:For the clocking data of RAM2 given by the program command which is read out of ROM1, the bit data of the 2nd dividing counter 11 passing through gates G1... and G1'... via adder circuit 3 receives the addition operation, and the clocking results of hour, minute, second and others are displayed in sequence at display part 6. The division output of counter 9 is transferred to counter 11 from counter 9 via AND gate 12 the open/close of which is controlled with the control output given through inverter 13 of instruction decoder 4 and via FF10 which is controlled by the clock pulse. Gates G1... and G1'... are opened via decoder 4. And the data transfer is inhibited from counter 9 to counter 11 while the addition operation is carried out based on the contents of counter 11. Thus the watch malfunction due to the change of the data transfer can be prevented with a simple constitution.
申请公布号 JPS55162084(A) 申请公布日期 1980.12.17
申请号 JP19790069988 申请日期 1979.06.06
申请人 CASIO COMPUTER CO LTD 发明人 HOSHII TOSHIFUMI;MURANAGA YOSHINOBU
分类号 G04G3/00;G04G99/00 主分类号 G04G3/00
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