发明名称 TRATAMIENTO MEJORADO DE LOS DATOS DE ENTRADA Y DE SALIDA DE UN ORDENADOR
摘要 <p>A digital computer has a master clock for generating master clock pulses at a first frequency and has a counter for counting secondary clock pulses having a frequency less than the frequency of the master clock pulses. The secondary clock pulses are counted and used in the assignment of real times to bytes of input data, and in the comparison of real times with desired output times assigned to binary output data. The input data preferably is placed in a FIFO stack and the output data in a self-sorting stack. The sorting in the output stack occurs between changes in count in the counter containing the secondary clock pulses.</p>
申请公布号 ES492342(D0) 申请公布日期 1980.12.16
申请号 ES19420004923 申请日期 1980.06.11
申请人 FORD MOTOR COMPANY 发明人
分类号 G05B1/01;F02D41/24;F02D45/00;G05B15/02;G06F7/24;G06F7/78;G06F13/20;G06F15/78;G06F19/00;(IPC1-7):06F3/00;06F1/04 主分类号 G05B1/01
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