| 摘要 |
PURPOSE:To enable phase control of n sets of signals in timesharing manner, by picking up the leading and trailing phases of each signal corresponding to n sets of signals input with multiplication during one sampling in time sharing manner, and renewing the content of phase state memory circuit. CONSTITUTION:Signals of n sets input with multiplication during one sampling are distributed at the multiplexer 20, and the leading and trailing of the distrubuted signal are detected 2, 3 based on the #i-th signal from input memory circuits 1-1... 1-n and the #i-th signal input at present and they are fed to a control section 25. On the other hand, an output via a decoder from phase state memory circuits 8-1... 8-n present corresponding to n sets of signals and displaying the phase state on the content, and the output from the detecting sections 2 and 3 are received, and the control section 25 judges lead or lag of the leading and trailing phase of each signal. Thus, the leading phase and trailing phase of each signal corresponding to n sets of signals are picked up in time sharing manner, and the content of the circuits 8-1...8-n is renewed, enabling phase control in time sharing manner to n sets of signals by means of a single IC. |
