| 摘要 |
<p>Latch is formed by a pair of cross-coupled IGFETs (52, 54) with depletion mode transistors (44, 46) serving as differential loads and as switches to coule a memory bit line (3/9 and a reference voltage to the latch. Bit line (30) and latch nodes (48, 50) are initially precharged and balanced to a level, are enhancement threshold below the supply voltage V. Selection of a memory cell causes bit line (30) to discharge selectively depending on memory cell state. The latch is actuated by a clock for a short time (eg. 20-100nonosecs) after discharge starts.</p> |
