| 摘要 |
A digitally programmable ramp generator produces a substantially linear ramp along with an equivalent digital code by use of a multiplying digital to analog converter which drives an integrator which produces a ramp voltage. This ramp voltage is compared in a feedback circuit with a stairstep ramp (produced by another DAC driven by a counter) and the summed signal is coupled to the reference input of the multiplying DAC so that if there is a difference between the stairstep and the analog ramp the first converter will tend to catch up to the stairstep ramp. Such stairstep ramp is incremented by a comparator which senses when the reference voltage to the multiplying DAC approaches zero; each time this occurs there is an incrementing of the counter. Thus, the digital counter value is equivalent to the value of the analog ramp at any point in time.
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