| 摘要 |
PURPOSE:To make efficient data transfer possible by simultaneously performing data transfer among selected groups of function units in time-division mode. CONSTITUTION:In CPU and a memory unit, transmitting units A0-An-1 and receiving units B0-Bn-1 are connected independently to each other via bus controller 10. Bus controller 10 includes a transmitting register and receiving register, not shown in the figure, corresponding to each transmitting and receving units and a common bus for them. Controller 10 uses this data bus in time-division mode to establish data buses such as data transfer lines P0.1 and P2.n-1 between random units at the same time. |
