| 摘要 |
PURPOSE:To enhance the integrating degree of a complementary MOS semiconductor device by forming a narrow and deep groove by utilizing anisotropic Si etching in the boundary between a semiconductor substrate and a well layer and burying insulating layer in the groove to shorten the distance between diffused layers. CONSTITUTION:A resist pattern 12 having a hole corresponding to the boundary between an n-type Si substrate 11 and a p-type well layer 18 to be formed on the surface of the substrate 11 is formed thereon, ion milling is executed with Ar gas at the substrate 11 to etch the substrate 11 in narrow and deep manner to form an etched groove 13 having deeper depth than the layer 18, n-type impurity ion is implanted to the bottom surface of the groove 13 to form a field inversion preventive layer 14 thereon. Then, the pattern 12 is removed, heat treated, an SiO2 layer 16 is filled in the groove 13, and the SiO2 film 15 on the surface of the substrate 11 is simultaneously removed. Thereafter, it is etched to slightly reduce the height of the surface 17 of the layer 16, a p-type well layer 18 is diffused and formed on one substrate 11 isolated via the layer 16, and element regions are formed in the confronting substrate to form a C-MOS device. |
