发明名称 COMPARISON CIRCUIT
摘要 PURPOSE:To enable to diagnose independently of the number of input bits of compared objective, by taking a pair of exclusive logical sums between the compared instruction signal and the compared objective signal, delivering them, and detecting a fixed fault through the output at the final stage. CONSTITUTION:With diagnostic state, an external signal 6 is made to ''1'', and each comparison instruction signal ii (where; i=1...n) and a comparison objective signal 2i are kept the same value, then the output of an exclusive logical sum circuit 31 is at ''1'', this is delivered to make the output of an exclusive logical sum circuit 32 to ''1'' and further the output of an exclusive logical sum circuit 33 to ''1''. Thus, the output of ''1'' is propagated to the final state, circuit 3n, and all the output of exclusive logical sums are at ''1''. If any one in the circuit 3j has a fixed failure of ''0'', the output of the final stage 3n is at ''0'' to enable the detection of the fixed failure. Thus, diagnosis can be made independently of the number of input bits of comparison objective.
申请公布号 JPS55154633(A) 申请公布日期 1980.12.02
申请号 JP19790063028 申请日期 1979.05.22
申请人 NIPPON ELECTRIC CO;NIPPON TELEGRAPH & TELEPHONE 发明人 TAKAO KOUJI;TACHIBANA MASATOSHI
分类号 G06F11/22;G06F7/02;G06F7/04;G06F11/16 主分类号 G06F11/22
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