| 摘要 |
PURPOSE:To avoid a logical decision error without requiring an expensive multiplier by composing a circuit of a polarity decision unit, adder, subtracter and gate circuit. CONSTITUTION:A modulated wave received as a 8-phase phase-modulated wave is output in the form of demodulated signals (x) and (y) through demodulator 7. Signals (x) and (y) are input to signal polarity decision units 10 and 11, and also to adder 8 and subtracter 9 respectively. For example, when signals (x) and (y) are equal in polarity, exclusive-OR gate EX outputs logic ''0'' and the polarity decision result output of signal polarity decision unit 13 as to the output of subtracter 9 is sent out as output D2 from OR gate 01. Therefore, when y<=x, logic ''1'' is output and when y>x, logic ''0'' is output. Further, (x) and (y) differ in polarity, gate EX outputs logic ''1'' and the decision result outut of signal polarity inverter 12 with regard to the output signal of adder 8 is sent out as output D2. Therefore, logic ''1'' when y>=-x or logic ''0'' when y<-x is output. |
