| 摘要 |
PURPOSE:To enable to reduce the storage of error, by adding the difference between the changed value and the maximum display enable value to the next changed value. CONSTITUTION:The circuit comprises the A-D conversion input terminal 1, the first register 2, control unit 3, the second register 4, output terminal 5, the third register 3 6, the fourth register 7 containing maximum display enable value DELTAXx, flag 8 indicating minus sign, and flag 9 indicating whether or not the data output before is DELTAXx. With this constitution, the value not displayed before in the register 6, that is, the error of transmission data is sequentially added, and since the sum of the error and DELTAXk (increment between the digital values Xk-1 and Xk at sample time Tk-1 and Tk) is compared with DELTAXx, if the increment DELTAXn+3<DELTAXx like the sample time Tn+3, the error is cancelled by DELTAXx-DELTAXn+3, to avoid the storage of error and to reduce the error. |
