| 摘要 |
PURPOSE:To prevent the occurrence of a latch-up phenomenon in C-MOS by providing a high concentration area of the same inductive type as the substrate region between the substrate region and the reverse conductive type region provided on the substrate region. CONSTITUTION:An N<+>-type region 42 is formed on the main surface of N<+>-type semiconductor substrate 41, and a P-type region 43 is formed on the surface region of a section on the above region 42. When performing a diffused formation of the above region 43, the impurities of the substrate 41 are diffused within the region 42 contacting to the substrate 41, and an N<+>-type region 56 is formed. Hence, in case the C-MOS is formed on the substrate 41, as the series resistance value in the substrate 41 and the region 56 is low, the voltage drop sufficient to give a PNP transistor an active condition to change a P-type region 46 to an emitter, an N<+>- type region 41 and 56 to a base P-type region 43 to a collector, does not occur due to the above-mentioned resistance. Further, as the equivalent resistance is extremely small, a latch-up phenomenon will become hard to occur. |
