| 摘要 |
PURPOSE:To reduce arithmetic in frequency by dividing binary-coded data into partial bits and by storing a readable/writable memory with multiplication results of data by all integers expressed within a number of the partial bits. CONSTITUTION:Data (x) from input terminal 11 are multiplied by 2M<o> in multiplier 19 and supplied to multiplication part 21, the multiplication result of which is supplied as write data to RAM14 via switch 22. Once writing to RAM14 ends, partial-bit pattern aij of data ai to be multiplied by data (x) is generated by data generator 17 from the low-order bit side and RAM14 is addressed by the partial bit and read. The product of this read (x) and the partial bit is supplied to adder 32 by way of switch 31. The output of this adder 32 is digit-shifted as many times as the number of digits of the partial bits and also added to the partial product read next. |
