| 摘要 |
PURPOSE:To shorten the time of diagnosis by making it possible to diagnose a data bit and check bit at a time. CONSTITUTION:In case of diagnostic operation, diagnostic mode signal DS is set to ''1''. Next, eight bits of write register WDR are all set to ''0'' and check bit control signal WS is set to ''0'' before putting memory unit M' into write operation. Namely, ''00000000'' is written in memory circuit MM and ''0'' in memory circuit MC in this case. Next, eight bits of comparing data register N are all set to ''0''. At this time, error detection signal RS shows ''0''. Thus, the read operation is carried out. When eight bits of read data bits RD and all ''0'' and check bit RC is ''0'', error detecting circuit C' regards the logic of signal ES as nonerror logic in case that signal DS is ''1''. Next, eight bits of register WDR are all set to ''1''; in case that signal WS is ''1'', the logic of signal ES is similarly regarded as nonerror logic when bits RD are all ''1'' and bit RC is ''1''. |
