| 摘要 |
<p>PROBLEM TO BE SOLVED: To provide a semiconductor device, in which amounts of delay of clock signals being supplied to plural synchronization circuits are made equal. SOLUTION: Internal circuits 54 to 60 respectively include clock-adjusting circuits 72, 76, 80 and 84 to adjust the phases of clock signals given by a clock buffer 52. Even if differences are generated in the amount of delay in the clock signals caused by the wiring of clock wirings 64 to 70, the delay is adjusted for each internal circuit and operations of synchronization circuits 74, 78, 82 and 86, which are included in the circuits 54 to 60, respectively, are improved.</p> |
