发明名称
摘要 A receive control portion activates each of VCOs, and then sets a reference dividing ratio Ntyp in the programmable divider. With each of the VCOs active, the receive control portion determines whether the PLL circuit locks or not based on a signal inputted during this time. Based on the determination result, the receive control portion then creates pattern data in a first table. A second table is previously stored in memory. Written into the second table is an optimal VCO for each pattern. The receive control portion determines the optimal VCO corresponding to the created pattern data referring to the second table. This allows the receiver to optimally select a VCO at high speed.
申请公布号 JP3250796(B2) 申请公布日期 2002.01.28
申请号 JP19980144849 申请日期 1998.05.26
申请人 发明人
分类号 H04B1/26;H03B5/12;H03B5/32;H03J1/00;H03L7/099;H03L7/10;(IPC1-7):H04B1/26 主分类号 H04B1/26
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