发明名称 System providing multiple fetch bus cycle operation
摘要 In a system which includes a common bus to which a plurality of units are connected for the transfer of information, such as a data processing system, information may be transferred by the highest priority requesting unit during an asynchronously generated bus transfer cycle. Logic is provided for enabling a multiple fetch operation in which the master unit requesting multiple words of information from the slave unit during a first bus transfer cycle may receive such information from the slave unit during a series of later slave generated bus cycles. Logic is provided for enabling any other units to communicate over the common bus during the time between the first cycle and such last cycle during which the slave unit responds, thereby enabling at least two pairs of units to communicate with each other respectively, in an interleaved manner.
申请公布号 US4236203(A) 申请公布日期 1980.11.25
申请号 US19780867270 申请日期 1978.01.05
申请人 HONEYWELL INFORMATION SYSTEMS INC 发明人 CURLEY, JOHN L;JOHNSON, ROBERT B;LEMAY, RICHARD A;NIBBY, CHESTER M JR
分类号 G06F13/00;G06F13/16;G06F13/368;G06F13/37;G06F13/42;(IPC1-7):G06F1/04 主分类号 G06F13/00
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