发明名称 |
INTEGRIERTE SCHALTUNG MIT EINER LOGISCHEN SCHALTUNG AUS KOMPLEMENTAEREN TRANSISTOREN |
摘要 |
An integrated logic circuit with complementary transistors which is constructed from cells which form reproductions of logic equations, in which each cell has at least three transistors arranged one next to the other in a row and three complementary transistors arranged one next to the other. Series arrangements of transistors or transistor circuits in one row corrugated to parallel arrangements of transistors or transistor circuits in the other row. This arrangement results in compact layouts which are easy to design with computer assistance. The arrangement is particularly useful for MSI and LSI circuits. |
申请公布号 |
AT359560(B) |
申请公布日期 |
1980.11.25 |
申请号 |
AT19740000692 |
申请日期 |
1974.01.29 |
申请人 |
N.V. PHILIPS' GLOEILAMPENFABRIEKEN |
发明人 |
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分类号 |
H01L21/822;H01L21/82;H01L27/02;H01L27/04;H01L27/082;H01L27/092;H03K19/082;H03K19/0948;H03K19/096;(IPC1-7):03K19/08;01L27/04 |
主分类号 |
H01L21/822 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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