发明名称 MEMORY DEVICE
摘要 PURPOSE:To omit both serial/parallel (S/P) and P/S converting circuits for reduction of the logic circuit scale by using a selector which selects the correspondence between the data signal received from a memory array and the data signal of a memory device by the parallel input/output and the serial input/output in accordance with the mode switch signal and the selection signal. CONSTITUTION:A selector 12 which selects the correspondence between the data signal of a memory array 11 and the data signal of a memory device in accordance with the mode switch signal P/the inverse of S (between parallel/ serial input/output modes) and selection signals S0 and S1 is added into a mem ory 1 to attain the actions same as those of the S/P and P/S converting circuits. Thus it is possible to obtain a memory device that requires no S/P nor P/S converting circuit and is capable of the parallel input/output and the serial input/output respectively.
申请公布号 JPH01144119(A) 申请公布日期 1989.06.06
申请号 JP19870303046 申请日期 1987.11.30
申请人 NEC CORP 发明人 ISHIKAWA TORU
分类号 G06F5/00;G06F12/00;G06F12/04;H03M9/00 主分类号 G06F5/00
代理机构 代理人
主权项
地址