| 摘要 |
PURPOSE:To obtain the carrier reproducing circuit having the functions which can detect asynchronism of the carrier reproducing PLL and that of clock synchronous circuit, by adding one detection circuit. CONSTITUTION:The digital phase modulation wave input to the input terminal 1 is in phase comparison with the reproduced carrier fed from PLL5 at the demodulator 6, and the output is in A/D conversion and output from the terminals 2, 2' as the digital demodulation signal. The output of the A/D converter 62 is fed to the clock synchronous circuit 7 and the clock in synchronizing with the demodulation data is obtained as the output of VCO75. This clock signal is adjusted of the phase by the phase shifter 8 and then formed of the pulse width at the circuit 9 and fed to PLL5. The A/D conversion output of the demodulator 6 is input to the inverse modulator 4, and the input signal is in inverse modulation with the data signal. The output of the inverse-modulator 4 is fed to PLL5 as the carrier of nonmodulation. The input signal of VCO54 in the PLL circuit 5 is branched and detected at the detection circuit 10, then output as the signal representing asynchronized state. |
