| 摘要 |
PURPOSE:To hold the peak value of input signal pulse even to the input signal lower in the stability of repetitive frequency, by producing the sample signal from the input signal pulse itself and by the sample hold. CONSTITUTION:The signal 8 input from the signal input terminal 1 is input to the delay circuit 2 and the comparator 3. The output 10 of the comparator 3 and the prediction gate signal 11 from the prediction gate signal input terminal 4 are input to the AND circuit 5 and the sample signal 12 eliminating excessive pulses can be obtained. The delay circuit 2 is a circuit to compensate the difference between the leading time of the signal 8 and that of the sample signal 12. Accordingly, the signal 9 after passing through the delay circuit 2 is always in synchronizing with the sample signal 12, it is sample-held at the sample hold circuit 6 and it is output from the output terminal 7 as the stable output signal waveform 13. |
