发明名称 |
Time-shared, multi-phase memory system with error checking and data correcting |
摘要 |
A multi-phase, bit addressable, variable field memory system partitioned into a plurality of individually addressable memory stacks and employing time-shared accessing circuitry as well as time shared error detection and data correction means, whereby serial memory stack accessing along with serial error checking and correction are achieved without significantly increasing the overall memory accessing time over that obtained for parallel accessing.
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申请公布号 |
US4234918(A) |
申请公布日期 |
1980.11.18 |
申请号 |
US19770801869 |
申请日期 |
1977.05.31 |
申请人 |
BURROUGHS CORPORATION |
发明人 |
CHU, KE-CHIANG;SHARP, RICHARD S. |
分类号 |
G06F11/10;G06F12/04 |
主分类号 |
G06F11/10 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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