| 摘要 |
An error detector provides an output pulse whenever an error is detected in the framing pattern of a digital transmission system. A sample timer provides a sample pulse at the beginning of each sample interval and a sample clock pulse during the sample pulse. The sample interval includes a plurality of frames and the sample pulse occurs intermediate of the framing pattern. A logic arrangement is responsive to the error output pulse, the sample clock pulse and the sample pulse for providing an alarm indication when the number of error pulses equals or exceeds a first predetermined number during a sample interval. Conversely, the logic arrangement eliminates the alarm indication if the number of errors in a subsequent sample interval is less than a second predetermined number.
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