发明名称 Techniques to create low K ILD for beol
摘要 One aspect of the present subject matter relates to a method for forming an interlayer dielectric (ILD). In various embodiments of the method, an insulator layer is formed, at least one trench is formed in the insulator layer, and a metal layer is formed in the at least one trench. After the metal layer is formed, voids are formed in the insulator layer. One aspect of the present subject matter relates to an integrated circuit. In various embodiments, the integrated circuit includes an insulator structure having a plurality of voids that have a maximum size, and a metal layer formed in the insulator structure. The maximum size of the voids is larger than the minimum photo dimension of the metal layer such that a maximum-sized void is capable of extending between a first and second metal line in the metal layer. Other aspects are provided herein.
申请公布号 US7190043(B2) 申请公布日期 2007.03.13
申请号 US20040931140 申请日期 2004.08.31
申请人 MICRON TECHNOLOGY, INC. 发明人 BHATTACHARYYA ARUP;FARRAR PAUL A.
分类号 H01L29/00;H01L21/316;H01L21/768;H01L23/48;H01L23/522;H01L23/532 主分类号 H01L29/00
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