| 摘要 |
PURPOSE:To enhance the scale of integration by a process wherein, in forming a region of high impurity concentration in the low withstand voltage region of a bipolar power IC having high and low withstand-voltage regions, a stretching diffusion is effected after an ion implantation to simultaneously form an isolation region. CONSTITUTION:The surface of a p-type Si substrate 10 is photoetched to form a well portion 12 which constitutes a high withstand-voltage region. A diffusion of P or Sb is effected in this well portion 12 to form an n<+>-type region 14A. At the same time, an n<+>-type 16A of Sb dope constituting a low withstand-voltage region is formed at the other surface to permit an epitaxial growth of n<->-type layer over the entire region. Then, impurities are again diffused in the regions 14A and 16A to form embedded regions 14 and 16. Thereafter, an n<+>-type region 20A is formed in the layer 18 at a position above the region 16. In this state, attention must be drawn not to permit a horizontal spreading by P ion implantation. Thereafter, B is diffused in the area between the high and low withstand-voltage region to form a p<+>-type isolation region 22 thereby to separate the layer 18 into inlands 18a, 18b. simultaneously, the region 20A is stretched to form a region 20 integral with the region 16. |
