| 摘要 |
PURPOSE:To quicken the transfer of signals from digit lines to data bus lines by providing between both the lines an amplifying circuit and a signal transfer method controlled by the output signal of a column decoder. CONSTITUTION:Once rising after signals appear at digit lines Di and Di', output Yi of a column decoder is transmitted to amplifying circuit CA consisting of MISTRs Qi5-Qi7 by way of MIS transistor TRs Qi1 and Qi2. Signals amplified by circuit CA brought under the control of output Yi are sent to a couple of data bus lines DB and DB' by way of MISTRs Qi3 and Qi4. In this circuit constitution, no capacity is formed between the digit lines and data bus lines. Therefore, the signal of an unselected digit line never propagates through data bus lines as noises. For the purpose, the time of signal transfer can be shortened by increasing the current performance of circuit CA consisting of those TRs with TRs Qi5-Qi7 increased in dimension. |
