发明名称 DIVIDING CIRCUIT HAVING FREQUENCY SHIFT FUNCTION OF INPUT PULSE
摘要 PURPOSE:To realize both the high integration and the low power consumption to ensure the high-speed operation, by supplying the input pulse signal directly to the input control type binary counter circuit through the two binary counter circuits which are connected in series. CONSTITUTION:Input pulse signal fIN is applied to the input terminal of front- step counter 11 of the binary counters 11 and 12 which are connected in series, and the output signal is supplied to input control type binary counter circuit 21 from end Q2 of rear-step counter 12. At the same time, the output signal is applied to the clock input terminals of 1-bit shift registers 14 and 15 which are connected in series. Here change-over signal CHANGE which has the level inversion with every fixed period is applied to registers 14 and 15 via inverter 16, and the outputs of Q3 and Q4' are sent to circuit 21 along with the shift signal via inverter 18 and through NAND gate 17. As a result, the high-speed operation becomes possible through the high integration and the low power consumption realized.
申请公布号 JPS55145440(A) 申请公布日期 1980.11.13
申请号 JP19790052332 申请日期 1979.04.27
申请人 TOKYO SHIBAURA ELECTRIC CO 发明人 TAKADA MINORU;SUZUKI YASOJI
分类号 H03K23/52;H03K23/64 主分类号 H03K23/52
代理机构 代理人
主权项
地址