| 摘要 |
PURPOSE:To reduce hardware in scale by providing a circuit which receives outputs of error detecting circuits and the signal of an error inhibiting circuit outputting an error inhibition signal and outputs selectively an error control signal to an error register. CONSTITUTION:Error inhibiting circuit 61, applied with error signals 39-41 detected by error detecting circuits 36-38, outputs error inhibition signals 61c-61e from its own shift registers 61a and 61b. Those inhibition signals 61c-61e and error signals 39-41 are applied to error selecting circuit 62, where error signals 40 and 41 and inhibition signals 61c-61e are AND-ed by inhibiting gates 62a and 62b. Further, the outputs of gates 62a and 62b, and error signal 39 are AND-ed by AND gate 62c to output error control signal 44 from selecting circuit 62 to error register 42, which exercises control over whether error signals 39-41 input to register 42 are fetched or not, thereby reducing the hardware of the error control circuit in scale. |
