| 摘要 |
PURPOSE:To obtain a memory device with a high write-in efficiency and a quick reading speed by providing inside the drain of IGFET a conductive layer separated from the source and the drain there. CONSTITUTION:The ''ON'' and ''OFF'' of FET on a p-type source and a drain 32 and 33 are detected and read out. At this time, an n-layer 34 inside a drain 33 serves as the control gate of a p-channel. When an inverse voltage, which will have a breakdown between a layer 34 and a layer 33, is given to the layer 34, a depletion layer by the layer 34 expands to the layer 33, it contacts to the depletion layer of the layer 31, and the p-layer 33 is separated into two, thereby giving an ''OFF'' position. Therefore, the selection of a memory cell can be controlled by the FET having the n-layer used as a gate. This constitution gives false 1 transistor/1 cell construction and the degree of integration and the delayed reading speed of the conventional p-channel floating gate type memory storage can be improved. Also the low write-in efficiency of an n-channel type can be improved by avalanche injecting. |
