| 摘要 |
PURPOSE:To improve performance and yield rate at the least process of work by correctly matching between a gate edge of a high dielectric strength IGFET and a pinch resistance layer, and between E(enhancement)/D(depression) type FE gate edge and a diffusion layer taking advantage of self-matching method. CONSTITUTION:An opening is provided at the two-layer film 42 of an SiO2 71 and an Si3N4 72 on a p-type substrate 1, and B ion is injected. An oxidized layer 43 and a p<+>-layer 44 are formed by oxidation, and an element is isolated. Excluding the Si3N4 72, p ion is injected after oxidation. Then a window is selectively opened and oxidized, and a pinch resistance layer 50 is obtained at the opening section by the diffusion of SiO2 49 and P. Subsequently, a doped channel 52 and a polycrystalline Si gate 53 is selectively formed by injecting As ion on the region Y, and after selectivety injecting B ion, p-type layer 59 is enlarged as far as to the point immediately below the gate 53 by heating it in a nonoxidized atmosphere. Then an opening is made on the oxidized film, and an n<+>-film 60 is formed by self-matching. Lastly, it is covered by an oxidized film 61, an opening is made and Al wiring is provided. With this method used, it is unnecessary to leave a margin at the width Al electrode, there occurs no floating capacity, and it enables a high-speed operation. |
