| 摘要 |
PURPOSE:To eliminate the loss time of a code inverting circuit and to ensure a high-speed operation of a multiplier by supplying the input data as they are to the 1st and 2nd registers with no inversion of codes. CONSTITUTION:When a selection signal CS is set at '1', the inverse of X is delivered from an inverter 7 and the multiplication of the inverse of XY is carried out by a partial product generating circuit 6 of a multiplier 4'. At the same time, the signal CS is supplied to each AND circuit 9 and therefore Y is delivered to a half adder 7 and a full adder 10 respectively to be added together by both adders. Thus the inverse of X.Y is obtained. Thus it is possible to obtain a multiplier which produces no loss time for inversion of codes. |
