发明名称 INHIBIT TIMING TEMPERATURE CONTROL SYSTEM OF CORE MEMORY UNIT
摘要 PURPOSE:To improve reliability by increasing the operation tolerance of a core memory unit by adding a capacitor, resistance and temperature sensing resistance element to an inhibit driving circuit and by varying the time constant of the circuit according to a temperature. CONSTITUTION:Input pulse A is inverted by logic circuit 25 into input pulse B to logic circuit 20. The rise time of its waveform depends upon capacitor 23, resistances 21 and 24, and temperature sensing element 22, and waveforms 27a, 28a and 29a can be obtained at a high temperature, normal temperature and low temperature. Output pulse C of logic circuit 20 obtained by inverting the pulse is input to logic circuit 17 and waveform-shaped pulse E is output via pulse D. Once supplied with pulse E, logic circuit 10 drives inhibit circuits 2 and 3 according to write information WI to make nearly constant currents I1 and I2 flowing through core 1 covering a broad temperature range. Therefore, the operation tolerance of the core memory unit increases and its reliability improves.
申请公布号 JPS55139684(A) 申请公布日期 1980.10.31
申请号 JP19790036843 申请日期 1979.03.30
申请人 TOHOKU METAL IND LTD 发明人 OOMIYA KENICHI
分类号 G11C11/02;G11C11/063;(IPC1-7):11C11/063 主分类号 G11C11/02
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